Question 1 
In the following truth table, V = 1 if and only if the input is valid.
What function does the truth table represent?
Priority encoder  
Decoder  
Multiplexer  
Demultiplexer 
Discuss it
Question 1 Explanation:
Since there are more than one outputs and number of outputs is less than inputs, it is a Priority encoder
V=1 when input is valid and for priority encoder it checks first high bit encountered. Except all are having at least one bit high and ‘x’ represents the “don’t care” as we have found a high bit already. So answer is (A).
Question 2 
Which one of the following expressions does NOT represent exclusive NOR of x and y?
xy + x' y'  
x ^ y' where ^ is XOR  
x' ^ y where ^ is XOR  
x' ^ y' where ^ is XOR 
Discuss it
Question 2 Explanation:
It is a simple De Morgan's laws question.
Question 3 
X  
X+Y  
X xor Y  
Y 
Discuss it
Question 3 Explanation:
The value of f(X, Y) is same as X for all input pairs.
We see from truth table –
Column x= f(x,y)
So , f(x,y)=x
Ans is (A) part.
Question 4 
b'd'  
b'd' + b'c'  
b'd' + a'b'c'd'  
b'd' + b'c' + c'd' 
Discuss it
Question 6 
The simplified SOP (Sum Of Product) form of the boolean expression (P + Q' + R') . (P + Q' + R) . (P + Q + R') is
(P'.Q + R')  
(P + Q'.R')  
(P'.Q + R)  
(P.Q + R) 
Discuss it
Question 6 Explanation:
See following (Source: http://clweb.csa.iisc.ernet.in/rahulsharma/gate2011key.html)
Question 7 
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
000  
001  
010  
011 
Discuss it
Question 7 Explanation:
P' = R
Q' = (P + R)'
R' = QR' Given that (P, Q, R) = (0, 1, 0), next state P', Q', R' = 0, 1, 1

D flip flop truth table
Initially (p,q,r) =(0,1,0)
D for p=R
D for q=NOT(p xor r)
D for r= (not)r.q
So Q(t+1) for(p,q,r)
p=>r=0 so p=0
q=> NOT(p xor r) => 1 so q=1
r=>(not)r.q => 1 so r=1
(p,q,r)=(0,1,1)
D  Q(t+1) 
0  0 
1  1 
Question 8 
Consider the data given in previous question. If all the flipflops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter?
3  
4  
5  
6 
Discuss it
Question 8 Explanation:
There are four distinct states, 000 → 010 → 011 → 100 (→ 000) so the answer is B
Question 9 
The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is
m2 + m4 + m6 + m7  
m0 + m1 + m3 + m5  
m0 + m1 + m6 + m7  
m2 + m3 + m4 + m5 
Discuss it
Question 10 
(P(XOR)Q(XOR)R)'  
P(XOR)Q(XOR)R  
(P+Q+R)'  
P+Q+R 
Discuss it
Question 10 Explanation:
For 4 to 1 mux truth table
SEL INPUT O/P
p’q’r+p’qr’+pq’r’+pqr
pXORqXORr
Q  P  R  R’  R’  R  F 
0  0  X  X  X  1  1 
0  1  X  X  1  X  1 
1  0  X  1  X  X  1 
1  1  1  X  X  X  1 
Question 11 
What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?
(Q+R)'  
(P+Q)'  
(P+R)  
(P+Q+R)' 
Discuss it
Question 11 Explanation:
Answer is Option A.
The above question contains the NOR gates. Let's see what NOR gate does.
If A and B are the two inputs to the NOR gate, the NOR gate gives (A+B)' as the output.
Let's assign numbers to the Gates for the easy understanding.
In the 1st column there are 4 NOR Gates, number them as 1 to 4 ( top to down). In the 2nd column there are 2 NOR Gates, number them as 5 and 6 ( top to down). In the 3rd column there is only 1 NOR Gate, number it as 7. 1st numbered Gate gives output as : ( P + Q )' 2nd numbered Gate gives output as : ( Q + R )' 3rd numbered Gate gives output as : ( P + R )' 4th numbered Gate gives output as : ( R + Q )' 5th numbered Gate gives output as : (( P + Q )' + ( Q + R )')' = ((P + Q)'' . ( Q + R )'') ( De Morgan's law) = (P + Q ) . ( Q + R ) ( Idempotent Law, A'' = A) = (PQ + PR + Q + QR ) = (Q(1 + P + R) + PR) = Q + PR ( as, 1 + " any boolean expression" = 1 ) Similarly 6th numbered Gate gives output as : R + PQ (as this time R is common here) Now 7th numbered Gate gives output as : ((Q + PR) + (R + PQ))' = (Q( 1+P) + R(1+P))' = (Q+R)'
Question 12 
In the sequential circuit shown below,if the initial value of the output Q1Q0 is 00,what are the next four values of Q1Q0?
11, 10, 01, 00  
10, 11, 01, 00  
10, 00, 01, 11  
11, 10, 00, 01 
Discuss it
Question 12 Explanation:
We have t flip flop
Truth table of t flip flop
So q0 always inverted as t=1 always
So 1)q10=1
2)q0 =0
3)q0 =1
4)q0 =1
For q1 also t=1 always but clock is so we have to observe positive edge of clock I.e. when is q0 going from 0 > 1
1)q1 =1
2)q1 =1
3)q1 =0
4)q1 =0
So final combination q0q1>(11,10,01,00) Ans (A)
t  q 
0  q 
1  q’ 
Question 13 
What is the minimum number of gates required to implement the Boolean function (AB+C)if we have to use only 2input NOR gates?
2  
3  
4  
5 
Discuss it
Question 13 Explanation:
AB+C = (A+C)(B+C) = ((A+C)' + (B+C)')'
So, '3' 2input NOR gates are required.
Question 14 
In the Karnaugh map shown below, X denotes a don't care term. What is the minimal form of the function represented by the Karnaugh map?
A) B) C) D)
A  
B  
C  
D 
Discuss it
Question 15 
decimal 10  
decimal 11  
decimal 10 and 11  
any value > 2 
Discuss it
Question 15 Explanation:
As we can see 121 contains digit ‘2’ which can’t be represented directly in base ‘2’ (as digits should be less than base) so number system must have “r>2”.
Ans (D) part.
Question 16 
Given f_{1}, f_{3} and f in canonical sum of products form (in decimal) for the circuit
A) m(4, 6) B) m(4, 8) C) m(6, 8) D) m(4, 6, 8)
A  
B  
C  
D 
Discuss it
Question 16 Explanation:
From logic diagram we have f=f1.f2+f3
f=m(4,5,6,7,8).f2+m(1,6,15)(1)
from eq(1) we need to find such f2 so that we can get f=m(1,6,8,15)
eq(1) says we can get m(1,6,15) from f3 ,so only 8 left
now from option (a,b,d) we get (4,6), (4,8) ,(4,6,8) respectively for m(4,5,6,7,8)f2 which is not required as m4 is undesired.
But option (D) m(4,5,6,7,8)(6,8)+(1,6,15)
 m(6,8)+m(1,6,15)
 m(1,6,8,15)an
Question 17 
If P, Q, R are Boolean variables, then (P + Q')(PQ' + PR)(P'R' + Q') simplifies
PQ'  
PR'  
PQ' + R  
PR'' + Q 
Discuss it
Question 18 
How many 3to8 line decoders with an enable input are needed to construct a 6to64 line decoder without using any other logic gates?
7  
8  
9  
10 
Discuss it
Question 19 
Consider the following Boolean function of four variables:
f(w,x,y,z) = ∑(1,3,4,6,9,11,12,14)
The function is:
independent of one variables.  
independent of two variables.  
independent of three variables.  
dependent on all the variables. 
Discuss it
Question 20 
Let f(w, x, y, z) = ∑(0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are NOT equivalent to f?
x'y'z' + w'xy' + wy'z + xz  
w'y'z' + wx'y' + xz  
w'y'z' + wx'y' + xyz + xy'z  
x'y'z' + wx'y' + w'y 
Discuss it
Question 20 Explanation:
Question 21 
Define the connective * for the Boolean variables X and Y as: X * Y = XY + X' Y'. Let Z = X * Y.
Consider the following expressions P, Q and R. P: X = Y⋆Z Q: Y = X⋆Z R: X⋆Y⋆Z=1Which of the following is TRUE?
Only P and Q are valid  
Only Q and R are valid.  
Only P and R are valid.  
All P, Q, R are valid. 
Discuss it
Question 21 Explanation:
* is nothing but working as EX NOR here.Explanation:
P:
X= Y * Z =(Y XOR Z)’ =YZ + Y’Z’ =Y(XY + X’Y’)+Y’(XY+X’Y’)’ =XY+Y’((Y XOR X)’)’ =XY+Y’(Y XOR X) =XY+Y’(Y’X+X’Y) =XY+Y’X =X(Y+Y’) =XQ:
Y=X*Z =(X XOR Z)’ =X(XY + X’Y’) + X’(XY + X’Y’)’ =XY+X’(X’Y+XY’) =XY+X’Y =YR:
X * Y *Z WE HAVE SEEN FROM P Y*Z =X SO X * X
 NOT(X XOR X)=X’X’+XX
 1
Question 22 
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?
2^{n} line to 1 line  
2^{n+1} line to 1 line  
2^{n1} line to 1 line  
2^{n2} line to 1 line 
Discuss it
Question 22 Explanation:
We can use n1 selection lines , and using 0,1 and nth variable and its compliment to realize the function
So ans is 2^(n1):1 Part(C )
Question 23 
In a lookahead carry generator, the carry generate function G_{i} and the carry propagate function P_{i} for inputs A_{i} and B_{i} are given by:
P_{i} = A_{i} ⨁ B_{i} and G_{i} = A_{i}B_{i}The expressions for the sum bit S_{i} and the carry bit C_{i+1} of the lookahead carry adder are given by:
S_{i} = P_{i} ⨁ C_{i} and C_{i+1} = G_{i} + P_{i}C_{i} , where C_{0} is the input carry.Consider a twolevel logic implementation of the lookahead carry generator. Assume that all P_{i} and G_{i} are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the lookahead carry generator for a 4bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively:
6, 3  
10, 4  
6, 4  
10, 5 
Discuss it
Question 23 Explanation:
let the carry input be c0
Now,
c1 = g0 + p0c0 = 1 AND, 1 OR c2 = g1 + p1g0 + p1p0c0 = 2 AND, 1 OR c3 = g2 + p2g1 + p2p1go + p2p1p0c0 = 3 AND, 1 OR c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0 = 4 AND, 1 ORSo, total AND gates = 1+2+3+4 = 10 , OR gates = 1+1+1+1 = 4 So as a general formula we can observe that we need a total of " n(n+1)/2 " AND gates and "n" OR gates for a nbit carry look ahead circuit used for addition of two binary numbers.
Question 24 
The control signal functions of a 4bit binary counter are given below (where X is “don’t care”)
The counter is connected as follows:
Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:
0, 3, 4  
0, 3, 4, 5  
0, 1, 2, 3, 4  
0, 1, 2, 3, 4, 5 
Discuss it
Question 24 Explanation:
Initially A1 A2 A3 A4 =0000
Clr=A1 and A3
So when A1 and A3 both are 1 it again goes to 0000
Hence 0000(init.) > 0001(A1 and A3=0)>0010 (A1 and A3=0) > 0011(A1 and A3=0) > 0100 (A1 and A3=1)[ clear condition satisfied] >0000(init.) so it goes through 0>1>2>3>4
Ans is ( C) part.
Question 25 
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flipflops) will delay the phase of f by 180°?
A  
B  
C  
D 
Discuss it
Question 25 Explanation:
We assume the D flipflop to be negative edge triggered.
In option (A), during the negative edge of the clock, first flipflop inverts complement of ‘f’. But, the output of first flipflop has the same phase as ‘f’. Now, we give this output as input to the second flipflop, which is enabled by ‘clk’. Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.
In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output. So, (B) and (D) can’t be the answer.
In option (C), the first flipflop is activated by ‘clk’. So, the output of first flipflop has the same phase as ‘f’. But, the second flipflop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.
Therefore, (C) is the correct answer.
Please comment below if you find anything wrong in the above post.
In option (A), during the negative edge of the clock, first flipflop inverts complement of ‘f’. But, the output of first flipflop has the same phase as ‘f’. Now, we give this output as input to the second flipflop, which is enabled by ‘clk’. Thus, we get a double inverted output having same phase as the input. So, A is not the correct option.
In option (B) and (D), the output is inverted ‘f’. But, we want ‘f’ as the output. So, (B) and (D) can’t be the answer.
In option (C), the first flipflop is activated by ‘clk’. So, the output of first flipflop has the same phase as ‘f’. But, the second flipflop is enabled by complement of ‘clk’. Since the clock ‘clk’ has a duty cycle of 50% , we get the output having phase delay of 180 degrees.
Therefore, (C) is the correct answer.
Please comment below if you find anything wrong in the above post.
Question 26 
A  
B  
C  
D 
Discuss it
Question 26 Explanation:
F= PQ+P’QR+P’QR’S
=Q(P+P’+P’R’S)
USE PROP a+a’b=a+b
=Q(P+R+P’R’S)
=Q(P+P’R’S+R)
USE PROP a+a’b=a+b
=Q(P+R’S+R)
=Q(P+R+R’S)
USE PROP a+a’b=a+b
=Q(P+R+S)
=PQ+QR+QS
Ans (a)
Question 27 
Consider a 4to1 multiplexer with two select lines S1 and S0, given below
The minimal sumofproducts form of the Boolean expression for the output F of the multiplexer is
P'Q + QR' + PQ'R  
P'Q + P'QR' + PQR' + PQ'R  
P'QR + P'QR' + QR' + PQ'R  
PQR' 
Discuss it
Question 27 Explanation:
For 4 to 1 mux
=p’q’(0)+p’q(1)+pq’r+pqr’
=p’q+pq’r+pqr’
=q(p’+pr’)+pq’r
=q(p’+r’)+pq’r
=p’q+qr’+pq’r
Ans (a)
Question 28 
Let k = 2^{n}. A circuit is built by giving the output of an nbit binary counter as input to an nto2^{n} bit decoder. This circuit is equivalent to a
kbit binary up counter.  
kbit binary down counter.  
kbit ring counter.  
kbit Johnson counter. 
Discuss it
Question 28 Explanation:
For output of a decoder , only single output will be ‘1’ and remaining will be ‘0’ at the same time. So high output will give the count of the ring counter. Hence Ans is ( C) part.
Question 29 
Consider the equation (123)5 = (x8)y with x and y as unknown. The number of possible solutions is _____ .
1  
2  
3  
4 
Discuss it
Question 29 Explanation:
Changing (123) base 5 into base 10= 1*25+2*5+3*1=38
Changing x8 base y in decimal= x*y+8
Equating both we get xy+8=38
 xy=30
 possible combinations =(1,30),(2,15),(3,10)
Question 31 
Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.
f (x, y, a, b) { if (x is 1) y = a; else y = b; }Which one of the following digital logic blocks is the most suitable for implementing this function?
Full adder  
Priority encoder  
Multiplexer  
Flipflop 
Discuss it
Question 32 
The above sequential circuit is built using JK flipflops is initialized with Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycle is
001, 010, 011  
111, 110, 101  
100, 110, 111  
100, 011, 001 
Discuss it
Question 32 Explanation:
JK ff truth table
Initially Q2Q1Q0=000
Present state FF input Next state
So ans is ( C) part.
j  k  Q 
0  0  Q0 
1  0  1 
0  1  0 
1  1  Q0’ 
Q2  Q1  Q0  J2  K2  J1  K1  J0  K0  Q2  Q1  Q0 
0  0  0  1  0  0  1  0  1  1  0  0 
1  0  0  1  0  1  0  0  1  1  1  0 
1  1  0  0  0  1  0  1  1  1  1  1 
Question 33 
Let X denote the Exclusive OR (XOR) operation. Let ‘1’ and ‘0’ denote the binary constants. Consider the following Boolean expression for F over two variables P and Q:
F(P, Q) = ( ( 1 X P) X (P X Q) ) X ( (P X Q) X (Q X 0) )The equivalent expression for F is
P + Q  
(P + Q)'  
P X Q  
(P X Q)' 
Discuss it
Question 33 Explanation:
We need to simplify the above expression. As the given operation is XOR, we shall see property of XOR.
Let A and B be boolean variable.
In A XOR B, the result is 1 if both the bits/inputs are different, else 0.
Now,
( ( 1 X P) X (P X Q) ) X ( (P X Q) X (Q X 0) ) ( P' X P X Q ) X ( P X Q X Q ) ( as 1 X P = P' and Q X 0 = Q ) (1 X Q) X ( P X 0) ( as P' X P = 1 , and Q X Q = 0 ) Q' X P ( as 1 X Q = Q' and P X 0 = P ) PQ + P'Q' ( XOR Expansion, A X B = AB' + A'B ) This is the final simplified expression. Now we need to check for the options. If we simplify option D expression. ( P X Q )' = ( PQ' + P'Q )' ( XOR Expansion, A X B = AB' + A'B ) ((PQ')'.(P'Q)') ( De Morgan's law ) ( P'+ Q).(P + Q') ( De Morgan's law ) P'P + PQ + P'Q' + QQ' PQ + P'Q' ( as PP' = 0 and QQ' = 0 ) Hence both the equations are same. Therefore Option D.
Question 34 
xz' + xy + y'z  
xz' + xy + (yz)'  
xz + xy + (yz)'  
xz + xy' + y'z 
Discuss it
Question 34 Explanation:
Output from MUX 1=> Z’X+ZY’
Output from MUX2=> Y’(Z’X+ZY’)+YX
=>Y’Z+Y’Z’X+YX
=>Y’Z+X(Y’Z’+Y)
=>Y’Z+X(Y+Z’) USING A+A’B=(A+B)
=>Y’Z+XY+XZ’
So Ans is (A).
Question 35 
Given two three bit numbers a2a1a0 and b2b1b0 and c, the carry in, the function that represents the carry generate function when these two numbers are added is:
A  
B  
C  
D 
Discuss it
Question 35 Explanation:
For carry look ahead adder we know carry generate function
Where
As we are having two 3 bits number to add so final carry out will be C3
Putting value of Pi,Gi in 3
C3=(A2.B2)+(A1.B1)(A2+B2)+(A0.B0)(A1+B1)(A2+B2) (TAKING C0=0)
C3=A2.B2 +A1A2B1+A1B2B1+(A0B0)(A1A2+A1B2+B1A2+B1B2)
C3=A2B2+A1A2B1+A1B2B1+A0A1A2B0+A0A1B0B2+A0A2B1B0+A0B0B1B2
SO ANS IS (A) PART.
Question 36 
Consider the circuit in the diagram. The ⊕ operator represents ExOR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:
000  
001  
010  
101 
Discuss it
Question 36 Explanation:
The D flipflops are initialized to zeroes. This implies q0 = 0, q1 = 0 and q2 = 0 initially.
Clock cycle 1 : q0 = data = 1 , q1 = q0_{before} XOR q2_{before} = 0 XOR 0 = 0 , q2 = q1_{before} = 0
Clock cycle 2 : q0 = data = 0 , q1 = q0_{before} XOR q2_{before} = 1 XOR 0 = 1 , q2 = q1_{before} = 0
Clock cycle 3 : q0 = data = 0 , q1 = q0_{before} XOR q2_{before} = 0 XOR 0 = 0 , q2 = q1_{before} = 1
Clock cycle 4 : q0 = data = 1 , q1 = q0_{before} XOR q2_{before} = 0 XOR 1 = 1 , q2 = q1_{before} = 0
Clock cycle 5 : q0 = data = 1 , q1 = q0_{before} XOR q2_{before} = 1 XOR 0 = 1 , q2 = q1_{before} = 1
Clock cycle 6 : q0 = data = 0 , q1 = q0_{before} XOR q2_{before} = 1 XOR 1 = 0 , q2 = q1_{before} = 1
Clock cycle 7 : q0 = data = 0 , q1 = q0_{before} XOR q2_{before} = 0 XOR 1 = 1 , q2 = q1_{before} = 0
Clock cycle 8 : q0 = data = 0 , q1 = q0_{before} XOR q2_{before} = 0 XOR 0 = 0 , q2 = q1_{before} = 1
Clock cycle 9 : q0 = data = 0 , q1 = q0_{before} XOR q2_{before} = 0 XOR 1 = 1 , q2 = q1_{before} = 0
Thus, option (C) is correct.
Please comment below if you find anything wrong in the above post.
Question 37 
Consider a Boolean function f (w, x, y, z). suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i1 = (w1, x1, y1, z1) and i2 = (w2, x2, y2, z2) we would like the function to remain true as the input changes from i1 to i2 (i1 and i2 differ in exactly one bit position), without becoming false momentarily. Let f (w, x, y, z) = ∑(5,7,11,12,13,15). Which of the following cube
covers of f will ensure that the required property is satisfied?
w'xz, wxy', xy'z, xyz,wyz  
wxy,w'xz,wyz  
wx(yz)', xz, wx'yz  
wzy, wyz, wxz, w'xz, xy'z, xyz 
Discuss it
Question 38 
We consider the addition of two 2’s complement numbers b_{n1}b_{n2}...b_{0} and a_{n1}a_{n2}...a_{0}. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by c_{n1}c_{n2}...c_{0} and the carryout by c_{out}. Which one of the following options correctly identifies the overflow condition?
A  
B  
C  
D 
Discuss it
Question 38 Explanation:
When two signed 2's complement numbers are added, overflow is detected if:
We may note here that overflow occurs only when
CARRY_{in} ≠ CARRY_{out}
Overflow = C_{in} XOR C_{out}
or C_{n1} XOR C_{out}
 both operands are positive and the result is negative, or
 both operands are negative and the result is positive.

Question 39 
Consider numbers represented in 4bit gray code. Let h3h2h1h0 be the gray code representation of a number n and let g3g2g1g0 be the gray code of (n + 1) (modulo 16) value of the number. Which one of the following functions is correct?
A  
B  
C  
D 
Discuss it
Question 39 Explanation:
Write gray code (n) numbers from 0 to 15 and make another column for (n+1) numbers by shifting the next number on top. As shown in the table:
Now to determine the min terms for g3, g2, g1, g0, we see the '1s' in the corresponding columns. The digit they correspond to give the min terms of the function. Thus the answers we will be:
G3(h3h2h1h0)= ∑(4,12,13,15,14,10,11,9)
G2(h3h2h1h0)= ∑(2,6,7,5,4,12,13,15)
G1(h3h2h1h0)= ∑(1,3,2,6,13,15,14,10)
G0(h3h2h1h0)= ∑(0,1,6,7,12,13,10,11)
Thus g2 is given correctly in the options.
Read about KMaps to know about mapping, SOP and POS forms:
KMap (Karnaugh Map)
Watch NPTEL videos to learn more about:
Code converters
Logic Minimization Using Karnaugh Maps
Karnaugh Map Minimization Using Maxterms
This explanation has been contributed by Kriti Kushwaha.
Question 40 
f is independent of X  
f is independent of Y  
f is independent of Z  
None of X, Y, Z is redundant 
Discuss it
Question 40 Explanation:
[(XY’)’ NAND (YZ)’]= [(XY’)’ .(YZ)’]’
=XY’+YZ
SO NONE OF X,Y,Z IS REDUNDANT
Ans (D)
Question 41 
The hexadecimal representation of 657_{8} is
1AF  
D78  
D71  
32F 
Discuss it
Question 41 Explanation:
We can first convert to Binary, we get 110 101 111. Then convert binary to base 16, we get 1AF (0001 1010 1111).
(657)base 8=
Writing binary of each digit=> 110=6
=> 101=5
=> 111=7
Adding extra 0’s I beginning to make groups of 4 binary digits each
000110101111= 0001 1010 1111
In octal
 0001 =1
 1010 =A
 1111 =F
Question 42 
The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is
BC'D' + A'C'D + AB'D  
ABC' + ACD + B'C'D  
ACD' + A'BC' + AC'D'  
A'BD + ACD' + BCD' 
Discuss it
Question 43 
Consider the following circuit involving a positive edge triggered D FF.
Consider the following timing diagram. Let Ai represent the logic level on the line A in the ith clock period.
Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is
A0 Al A1' A3 A4  
A0 Al A2' A3 A4  
Al A2 A2' A3 A4  
Al A2' A3 A4 A5' 
Discuss it
Question 43 Explanation:
The Flip Flop used here is a Positive edge triggered D Flip Flop, which means that only at the "rising edge of the clock" flip flop will capture the input provided at D and accordingly give the output at Q. And at other times of the clock the output doesn't change. The output of D flip flop is same as input, i.e. Y=Q=D ( at the rising edge ).
Now, in the question above, 5 clock periods are given, and we have to find the output Q or Y in those clock periods.
First, let's derive the boolean expression for the Logic gate.
which is :
D = AX + X' Q'
Now,
In the 1st clock period, (i.e. when t = 0 to 1 )
here the clock has rising edge at t= 0, hence at this moment only, D flip flop will change its state.
In the 1st clock, X = 1, So, D = A. Now A logic line may have different levels at different clock periods, i.e. may be high or low, therefore we have to answer with respect to the ith clock period where Ai is the logic level ( high or low ) of logic line A in the ith clock.
So in the 1st clock period, A logic value should be A1 ( i.e. value of A in 1st clock period), but due to the delay provided by the Logic Gates ( Propagation Delay) the value of A used by Flip Flop is previous value of A only, i.e.it will capture the value of D resulted by using the logic line A in the 0th clock period, which is A0. Same happens with the value of X, i.e. instead of Xi, previous value of X is used in the in the ith clock period, which is Xi1.
Now, In the 1st clock period value of X is same as in the 0th clock, i.e. logic 1. So, X = 1 ,and A = A0, therefore, D = A0, and hence Q = Y = A0
Similarly we have to do for other clock periods, i.e. instead of taking Ai and Xi, Ai1 and Xi1 need to be taken for getting the output in the ith clock period.
In the 2nd clock period, (i.e. when t = 1 to 2 )
X = 1 ( value in the previous clock), So, D = A1 ( value of A in the previous clock) , therefore Q = Y = A1
In the 3rd clock period, (i.e. when t = 2 to 3 )
X = 0 ( value in the previous clock,see the timing diagram), So, D = Q' = A1' , therefore Q = Y = A1' ( because of the feedback line )
In the 4th clock period, (i.e. when t = 3 to 4 )
X = 1 ( value in the previous clock, ), So, D = A3 , therefore Q = Y = A3
In the 5th clock period, (i.e. when t = 4 to 5 )
X = 1 ( value in the previous clock ), so, D = A4 , therefore Q = Y = A4
Hence the output sequence is : A0 A1 A1' A3 A4
Question 44 
Consider the following circuit
The flipflops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:
A) B) C) D)
A  
B  
C  
D 
Discuss it
Question 44 Explanation:
Q_{0} will toggle in every cycle because Q_{0}' (Q_{0} complement) is fed as input to the D_{0} flip flop.
For the D_{1} flip flop, D_{1} = Q_{0} ⊕ Q_{1}' , i.e., Q_{0} XOR Q_{1}'.
So, the bit pattern Q_{0} Q_{1} will be :
Q_{0} Q_{1} 0 0 1 1 0 1 1 0 0 0 . . . . . .Thus, the transition sequence will be So, D would be the correct choice. Please comment below if you find anything wrong in the above post.
Question 45 
Consider the following floating point format
Mantissa is a pure fraction in signmagnitude form. The decimal number 0.239 × 2^{13} has the following hexadecimal representation (without normalization and rounding off :
0D 24  
0D 4D  
4D 0D  
4D 3D 
Discuss it
Question 46 
Consider the following floating point format
Mantissa is a pure fraction in signmagnitude form. The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0's are padded in while shifting a field. The normalized representation of the above number (0.239 × 2^{13}) is:
0A 20  
11 34  
4D D0  
4A E8 
Discuss it
Question 47 
The Boolean function x'y' + xy + x'y is equivalent to
x' + y'  
x + y  
x + y'  
x' + y 
Discuss it
Question 47 Explanation:
x’y’+xy+xy’
=(x’y’+y(x+x’))
=x'y’+y
=x'+y
Ans (d)
Question 48 
In an SR latch made by crosscoupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Q = 0, Q' = 1  
Q = 1, Q' = 0  
Q = 1, Q' = 1  
Indeterminate states 
Discuss it
Question 48 Explanation:
If both R reset and S set inputs are inactivated. It means made ‘0’, both Q and Q’ tend to be ‘1’. [NAND gate characteristic is that only when both inputs are 1,the output is 0.] The logic of the circuit (Q’ is complement of Q) not satisfied, and the final state at an instant after inputs R and S changed to ‘0’, is only a matter of chance. Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D) part.
Question 49 
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?
2  
3  
4  
5 
Discuss it
Question 49 Explanation:
We should get output 1 for values>=5
Making truth table for problem
Putting this in kmap and solving
Here crucial point is that we need to make pair of 8 elements using don’t cares also…so final expression is
A+BD+BC
A  B  C  D  Op 
0  0  0  0  0 
0  0  0  1  0 
0  0  1  0  0 
0  0  1  1  0 
0  1  0  0  0 
0  1  0  1  1 
0  1  1  0  1 
0  1  1  1  1 
1  0  0  0  1 
1  0  0  1  1 
1  0  1  0  X 
1  0  1  1  X 
1  1  0  0  X 
1  1  0  1  X 
1  1  1  0  X 
1  1  1  1  X 
 A+B(C+D)
Question 50 
Which are the essential prime implicants of the following Boolean function?
f(a, b, c) = a'c + ac' + b'c
a'c and ac'  
a'c and b'c  
a'c only  
ac' and bc' 
Discuss it
Question 50 Explanation:
Essential prime implicants are prime implicants that cover an output of the function that no combination of other prime implicants is able to cover i.e., if we delete such elements then the property of group, quad, octet is destroyed.
By drawing k map and by putting c on left side and a, b on right side we can find that a'c and ac' are essential prime implicants.
Question 51 
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2variable Boolean function f = T + R, without using any additional hardware ?
R to X, 1 to Y, T to Z  
T to X, R to Y, T to Z  
T to X, R to Y, 0 to Z  
R to X, 0 to Y, T to Z 
Discuss it
Question 51 Explanation:
For mux we will be having equation like z’x+zy(1)
Now putting X=R , Y=1 and Z=T in eq(1) we find
 T’R+T(1)
 T+T’R
 T+R (SINCE a+a’b=a+b)
Question 52 
Consider the partial implementation of a 2bitt counter using T flipflops following the sequence 02310, as shown below
To complete the circuit, the input X should be
1)
2)
3)
4)
Q2'  
Q2 + Q1  
(Q1 ⊕ Q2)'  
Q1 ⊕ Q2 
Discuss it
Question 52 Explanation:
From circuit we see T1=XQ1’+X’Q1(1)
AND T2=(Q2+Q1)’(2)
AND DESIRED OUTPUT IS 00>10>11>01>00
SO X SHOULD BE Q1Q2’+Q1’Q2 SATISFYING 1 AND 2.
SO ANS IS (D) PART.
Question 53 
A 4bit carry lookahead adder, which adds two 4bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using twolevel ANDOR logic.
4 time units  
6 time units  
10 time units  
12 time units 
Discuss it
Question 53 Explanation:
Let the input carry to the first adder be denoted by C1.
Now, to calculate C2 we need = P1C1 + G1 = 4 gate levels (P1 takes 2 gate levels)
to calculate S1 we need = P1 XOR C1 = 2 + 2 = 4 gate levels.
Since it is a Carry look ahead adder, computing C3 , S2 doesn't have to wait for carry output C2 from the previous adder as C2, C3 etc will get computed at the same time.
Now,
S2 is computed as = P2 XOR C2 = P2.C2' + P2'.C2
= P2 (P1.C1 + G1 )' + P2' (P1.C1 + G1) [ notice that we are not using the output carry from first adder C2 anywhere here ]
which can be implemented using 4 gate levels.
also C3 can be computed by using 4 gate levels and so on...
so the overall propagation delay is 4 gate level as the outputs at Si , Ci are available at the respective full adders after 4 gate levels = 4 time units.
To understand it with more clarity draw the carry look ahead adder circuit and then check it.
Question 54 
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
Θ(1)  
Θ(log n)  
Θ(n)  
Θ(n^{2}) 
Discuss it
Question 54 Explanation:
Number of gates used in ‘n’ bit array multiplier (n * n) = (2n – 1)
Each gate in the circuit has a unit delay.
Total delay = 1 * (2n – 1 ) = O(2n – 1) = O(n)
Thus, option (C) is correct.
Please comment below if you find anything wrong in the above post.
Each gate in the circuit has a unit delay.
Total delay = 1 * (2n – 1 ) = O(2n – 1) = O(n)
Thus, option (C) is correct.
Please comment below if you find anything wrong in the above post.
Question 55 
A 1input, 2output synchronous sequential circuit behaves as follows :
Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds.
zk  nk = 2. In this case, the output at the kth and all subsequent clock ticks is 10. nk  zk = 2. In this case, the output at the kth and all subsequent clock ticks is 01.What is the minimum number of states required in the state transition graph of the above circuit?
5  
6  
7  
8 
Discuss it
Question 55 Explanation:
The answer must be 5 to this question as we just need to count the difference of the number of 0's and 1's in the first k bit of a number. And we just need to count till this count reaches 2 or 2 (negative when number of 0's is less than number of 1's) . So, the possibilities are 2, 1, 0, 1 and 2 which represents the five states of the state transition diagram.
For state 2, the output of the circuit will be 01, for state 2, output will be 10 (both these states not having any outgoing transitions) and for other 3 states, output will be 00 as per the given description of the circuit.
Question 56 
The literal count of a boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz') is 4. What are the minimum possible literal counts of the productofsum and sumofproduct representations respectively of the function given by the following Karnaugh map ? Here, X denotes "don't care"
(11, 9)  
(9, 13)  
(9, 10)  
(11, 11) 
Discuss it
Question 57 
Consider the ALU shown below.
If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and  denote addition and subtraction respectively) ?
A + B, and A  B, but not A + 1  
A + B, and A + 1, but not A  B  
A + B, but not A  B, or A + 1  
A + B, and A  B, and A + 1 
Discuss it
Question 57 Explanation:
We can set value of k and c as 0 or 1
Two things we need to know
 If we take xor of any number with 1 we get it in its complement form.
 If we take xor of any number with 0 we get that number itself.
Question 58 
Consider the following circuit composed of XOR gates and noninverting buffers.
The noninverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns ?
1  
2  
3  
4 
Discuss it
Question 59 
Minimum sum of product expression for f(w, x, y, z) shown in Karnaughmap below is
_{yz}\^{wx}  00  01  11  10 
00  0  1  1  0 
01  x  0  0  1 
11  x  0  0  1 
10  0  1  1  x 
xz + y'z  
xz' + zx'  
x'y + zx'  
None of these 
Discuss it
Question 60 
Consider the following logic circuit whose inputs and function and output is f.
f(dx, y, z) f1(dx, y, z) f2(dx, y, z) f3(dx, y, z) = ?Given that
f1(dx, y, z) = ∑(d0, 1, 3, 5), f1(dx, y, z) = ∑(d6, 7) and f1(dx, y, z) = ∑(d1, 4, 5), f3 is :
∑(1, 4, 5)  
∑(6, 7)  
∑(0, 1, 3, 5)  
None of these 
Discuss it
Question 61 
Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is "the output of the multiplexor. EN is the enable input.
The function f(x, y, z) implemented by the above circuit is :
xyz'  
xy + z  
x + z  
None of these 
Discuss it
Question 61 Explanation:
F = (A1’A0’I0 + A1’A0I1 + A1A0’I2 + A1A0I3) * EN
F = (XYZ' +XYZ + Y'ZY + ZY')Z'
F = (XYZ' +XYZ + ZY'(Y + 1))Z'
F = (XYZ' +XYZ + ZY' * 1)Z'
F = (XY(Z’ + Z) + ZY’)Z’
F = (XY + ZY’)Z’
F = XYZ’ + 0
F = XYZ'
Thus, option (A) is correct.
Please comment below if you find anything wrong in the above post.
Question 62 
Let f(A, B) = A' + B. Simplified expression for function f(f(x + y, y)z) is :
x' + z  
xyz  
xy' + z  
None of these 
Discuss it
Question 62 Explanation:
Simplified expression for given function 'g' is :
g = f( f(x + y, y), z) g = f( ((x + y)’ + y), z) g = f( (x’y’ + y), z) g = f( ((y + y’) * (x’ + y)), z) g = f( (1 * (x’ + y)), z) g = f( (x’ + y), z) g = (x’ + y)’ + z) g = xy’ + z
Thus, option (C) is correct.
Please comment below if you find anything wrong in the above post.
Question 63 
Given the following Karnaugh map, which one of the following represents the minimal SumOfProducts of the map?
xy + y'z  
wx'y' + xy + xz  
w'x + y'z + xy  
xz + y 
Discuss it
Question 64 
Consider the following circuit with initial state Q0 = Q1 = 0. The D Flipflops are positive edged triggered and have set up times 20 nanosecond and hold times 0.
Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?
a  
b  
c  
d 
Discuss it
Question 64 Explanation:
Q_{0} = 0 (given) Therefore, Q_{0}' = 1
During the first clock cycle nothing will change since input doesn't come before rising edge of the clock cycle Q_{0}' becomes ’0’ on rising edge of next clock cycle. Therefore, for only one clock cycle D1 will be ‘1’.
Thus, option (C) is the answer.
Please comment below if you find anything wrong in the above post.
Question 65 
Consider the circuit given below with initial state Q0 =1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q_{2} + 2Q_{1} + Q_{0}
Which one of the following is the correct state sequence of the circuit?
1,3,4,6,7,5,2  
1,2,5,3,7,6,4  
1,2,7,3,5,6,4  
1,6,5,7,2,3,4 
Discuss it
Question 65 Explanation:
Initial value  Q0  Q1  Q2  2Q1+4Q2+Q0 
clk  1  0  0  1 
1  0  1  0  2 
2  1  0  1  5 
3  1  1  0  3 
4  1  1  1  7 
5  0  1  1  6 
6  0  0  1  4 
Question 66 
The simultaneous equations on the Boolean variables x, y, z and w,
have the following solution for x, y, z and w, respectively.
0 1 0 0  
1 1 0 1  
1 0 1 1  
1 0 0 0 
Discuss it
Question 66 Explanation:
We solve this question by putting in the options in the statements.
Statement 1 : x + y + z = 1
OPTION x y z w LHS LHS=1  A 0 1 0 0 1 Yes B 1 1 0 1 1 Yes C 1 0 1 1 1 Yes D 1 0 0 0 1 YesTill now, all the options are possible. Statement 2 : x y = 0
OPTION x y z w LHS LHS=0  A 0 1 0 0 0 Yes B 1 1 0 1 1 No C 1 0 1 1 0 Yes D 1 0 0 0 0 YesSince LHS ≠ 0, B is not possible. Statement 3 : x z + w = 1
OPTION x y z w LHS LHS=1  A 0 1 0 0 0 No C 1 0 1 1 1 Yes D 1 0 0 0 0 NoSince LHS ≠ 1, A and D are not possible. Statement 4 : x y + z' w' = 0
OPTION x y z w LHS LHS=0  C 1 0 1 1 0 YesThus, C is the correct option. Please comment below if you find anything wrong in the above post.
Question 68 
The following arrangement of masterslave flip flops has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),
1, 0  
1, 1  
0, 0  
0,1 
Discuss it
Question 68 Explanation:
Given P = 0 , J = 1 and k = 1
 JK flipflop toggles the input in ‘11’ state. Therefore, output of first flipflop at P is ‘1’.
 Initial value of P is input for D flipflop. So, D = 0 .Therefore, output of second flipflop at Q is ‘0’. Thus, option (A) is the answer. Please comment below if you find anything wrong in the above post.
Question 69 
Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is:
0, 1, 3, 7, 15, 14, 12, 8, 0  
0, 1, 3, 5, 7, 9, 11, 13, 15, 0  
0, 2, 4, 6, 8, 10, 12, 14, 0  
0, 8, 12, 14, 15, 7, 3, 1, 0 
Discuss it
Question 69 Explanation:
Refer http://en.wikipedia.org/wiki/Ring_counter#Johnson_Counter_.284bits.29
The four bit Johnson's counter connects the complement of the output of the last shift register to the input of the first register with shift distance=1 i.e 1 bit will shift/cycle
It will work as follows:
0000 //Last 0 complemented and fed as input to first register
1000
1100
1110
1111 //Last 1 complemented and fed as input to first register
0111
0011
0001
0000
Question 70 
A positive edgetriggered D flipflop is connected to a positive edgetriggered JK flipflop as follows. The Q output of the D flipflop is connected to both the J and K inputs of the JK flipflop, while the Q output of the JK flipflop is connected to the input of the D flipflop. Initially, the output of the D flipflop is set to logic one and the output of the JK flipflop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flipflop when the flipflops are connected to a freerunning common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the stateholding mode of the JK flipflop. Both the flipflops have nonzero propagation delays.
0110110...  
0100100...  
011101110...  
011001100... 
Discuss it
Question 70 Explanation:
Initially Q output of D  FF = 1
Initially Q output of JK  FF = 0
Now with the help of present state and next state table we can see what is happening in circuit.
 Toggle: J = K = 1
 Hold : J = K = 0
JK = 0
After clock 1 : D = 0 (D gets 0 as input from initial output of JK, so output = 0)
JK = 1 (J = K = 1 from initial output of D, so output would be toggled from 0 to 1)
After clock 2 : D = 1 (D gets 1 as input from previous output of JK, so output = 1)
JK = 1 (J = K = 0 from previous output of D, so output would be retained to 1)
After clock 3 : D = 1 (D gets 1 as input from previous output of JK, so output = 1)
JK = 0 (J = K = 1 from previous output of D, so output would be toggled from 1 to 0)
After clock 4 : D = 0 (D gets 0 as input from previous output of JK, so output = 0)
JK = 1 (J = K = 1 from previous output of D, so output would be toggled from 0 to 1)
After clock 5 : D = 1 (D gets 1 as input from previous output of JK, so output = 1)
JK = 1 (J = K = 0 from previous output of D, so output would be retained to 1)
Thus, the bit sequence generated at the Q output of the JK flip flop will be 0110110...Question 71 
Consider the operations
f(X, Y, Z) = X'YZ + XY' + Y'Z' and g(X′, Y, Z) = X′YZ + X′YZ′ + XY
Which one of the following is correct?
Both {f} and {g} are functionally complete  
Only {f} is functionally complete  
Only {g} is functionally complete  
Neither {f} nor {g} is functionally complete 
Discuss it
Question 71 Explanation:
A function is considered as functionally complete if it does not belong to T0,T1,L,M,S which are
Property 1: We say that boolean function f preserves zero, if on the 0input it produces 0. By the 0input we mean such an input, where every input variable is 0 (this input usually corresponds to the ﬁrst row of the truth table). We denote the class of zeropreserving boolean functions as T0 and write f ∈ T0.
Property 2: Similarly to T0, we say that boolean function f preserves one, if on 1input, it produces 1. The 1input is the input where all the input variables are 1 (this input usually corresponds to the last row of the truth table). We denote the class of onepreserving boolean functions as T1 and write f ∈ T1.
Property 3: We say that boolean function f is linear if one of the following two statements holds for f:
 For every 1value of f, the number of 1’s in the corresponding input is odd, and for every 0value of f, the number of 1’s in the corresponding input is even.
 For every 1value of f, the number of 1’s in the corresponding input is even, and for every 0value of f, the number of 1’s in the corresponding input is odd.
 F is not linear(see defn. of linear above)
 F is not monotone(see defn. of monotone above)
 F is not self dual as f(x,y,z) is not equal to –f(x,y,z)
Question 72 
The minimum number of JK flipflops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,...) is ________
0  
1  
2  
3 
Discuss it
Question 72 Explanation:
Ans = 3, mod 8 up counter using 3 JK flip flops. Ignore the output of LSB
Question 73 
The number of minterms after minimizing the following Boolean expression is _________.
[D′ + AB′ + A′C + AC′D + A′C′D]′
1  
2  
3  
4 
Discuss it
Question 73 Explanation:
Given Boolean expression is: [D′ + AB′ + A′C + AC′D + A′C′D]′ Step 1 : [D′ + AB′ + A′C + C′D ( A + A')]′ ( taking C'D as common ) Step 2 : [D′ + AB′ + A′C + C′D]′ ( as, A + A' = 1 ) : [D' + DC' + AB' + A'C]' (Rearrange) Step 3 : [D' + C' + AB' + A'C]' ( Rule of Duality, A + A'B = A + B ) : [D' + C' + CA' + AB']' (Rearrange) Step 4 : [D' + C' + A' + AB']' (Rule of Duality) : [D' + C' + A' + AB']' (Rearrange) Step 5 : [D' + C' + A' + B']' (Rule of Duality) :[( D' + C' )'.( A' + B')'] (Demorgan's law, (A + B)'=(A'. B')) :[(D''.C'').( A''.B'')] (Demorgan's law) :[(D.C).(A.B)] (Idempotent law, A'' = A) : ABCD Hence only 1 minterm after minimization.
Question 74 
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4bit ripplecarry binary adder is implemented by using full adders. The total propagation time of this 4bit binary adder in microseconds is
19.2 microseconds 
Discuss it
Question 74 Explanation:
A Ripple Carry Adder allows to add two nbit numbers. It uses half and full adders. Following diagram shows a ripple adder using full adders.
Let us first calculate propagation delay of a single 1 bit full adder. Propagation Delay by n bit full adder is (2n + 2) gate delays. [See this for formula]. Here n = 1, so total delay of a 1 bit full adder is (2 + 2)*1.2 = 4.8 ms Delay of 4 full adders is = 4 * 4.8 = 19.2 ms
Question 75 
The total number of prime implicants of the function f(w, x, y, z) = Σ(0, 2, 4, 5, 6, 10) is ________.
2  
3  
4  
5 
Discuss it
Question 75 Explanation:
Red,Blue and Green together make total three prime implicant.
As we know "A prime implicant of a function is an implicant that cannot be covered by a more general (more reduced  meaning with fewer literals) implicant. (Wikipedia)" we've to see only prime implicants . We can make group of four 1's as in the figure(green group) , a group of two 1's in blue and red .As we can't reduce it further so this is minimal representation of problem and hence total number of prime implicant =3. So answer (B) part.
Question 76 
Given the function F = P′ + QR, where F is a function in three Boolean variables P, Q and R and P′ = !P, consider the following statements.
S1: F = Σ (4, 5, 6) S2: F = Σ (0, 1, 2, 3, 7) S3: F = Π (4, 5, 6) S4: F = Π (0, 1, 2, 3, 7)Which of the following is true?
S1False, S2True, S3True, S4False  
S1True, S2False, S3False, S4True  
S1False, S2False, S3True, S4True  
S1True, S2True, S3False, S4False 
Discuss it
Question 76 Explanation:
After drawing K map of F = P` + QR ,we can find out S2 and S3 are TRUE.
Alternate Explanation :
P Q R = (!P + QR) 0 => 0 0 0 => 1+0.0 =1 =>Σ 1 => 0 0 1 => 1+0.1 =1 =>Σ 2 => 0 1 0 => 1+1.0 =1 =>Σ 3 => 0 1 1 => 1+1.1 =1 =>Σ 4 => 1 0 0 => 0+0.0=0 =>Π 5 => 1 0 1 => 0+0.1=0 =>Π 6 => 1 1 0 => 0+1.0=0 =>Π 7 => 1 1 1 => 0+1.1=1 =>Σ as sigma means 1 and pi means 0 therefore Σ = (0,1,2,3,7) Π = (4,5,6)
Question 77 
What is the minimum number of NAND gates required to implement a 2input EXCLUSIVEOR function without using any other logic gate?
3  
4  
5  
6 
Discuss it
Question 77 Explanation:
Pic Courtesy: http://www.electronicstutorials.ws/logic/logic_7.html
Other way around:
x XOR y = x’y+xy’ = x’y+xy’+xx’+yy’ = (x+y) (x’+y’)
Using NAND gates
F= (x+y)(xy)’ = x. (xy)’ + y. (xy)’
Taking compliment
F’= ( x. (xy)’ + y. (xy)’ )’ = (x. (xy)’)’. (y. (xy)’)
Compliment again
F=( (x. (xy)’)’. (y. (xy)’) )’
So Answer is B
Question 78 
Using a 4bit 2’s complement arithmetic, which of the following additions will result in an overflow?
(i) 1100 + 1100
(ii) 0011 + 0111
(iii) 1111 + 0111
(i) only  
(ii) only  
(iii) only  
(i) and (iii) only 
Discuss it
Question 78 Explanation:
When two signed 2's complement numbers are added, overflow is detected if:
 both operands are positive and the result is negative, or
 both operands are negative and the result is positive
 there is a carry out of the leftmost bit
Question 79 
The number (123456)_{8} is equivalent to
(A72E)16 and (22130232)4  
(A72E)16 and (22131122)4  
(A73E)16 and (22130232)4  
(A62E)16 and (22120232)4 
Discuss it
Question 79 Explanation:
(123456)8
=(001 010 011 100 101 110)2
To convert it into hexadecimal,make groups of 4
(1010 0111 0010 1110)
=(A72E)16
To convert it into base 4,make groups of 2
(10 10 01 11 00 10 11 10)
=(22130232)4
Question 80 
The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to
AC’+AB+A’C  
AB’+AC’+A’C  
A’B+AC’+AB’  
A’B+AC+AB’ 
Discuss it
Question 80 Explanation:
(A'BC + A'B'C) + (ABC' + AB'C') + AB'C A'C(B + B') + AC'(B + B') + AB'C A'C * 1 + AC' * 1 + AB'C A'C + AC' + AB'C A'C + A(C' + B'C) A'C + A(C' + B') A'C + AC' + AB'
Thus, option (B) is correct.
Please comment below if you find anything wrong in the above post.
Question 81 
Which of the following expressions is equivalent to (A⊕B)⊕C
(A+B+C)(A¯+B¯+C¯)  
(A+B+C)(A¯+B¯+C)  
ABC+A¯(B⊕C)+B¯(A⊕C)  
None 
Discuss it
Question 81 Explanation:
(A ⊕ B) ⊕ C By Solving, We get = (A ⊕ B)′ C + (A ⊕ B) C′ The above expression can be written as: = (A ⊙ B) C + (A ⊕ B) C′ Now, = (AB + A′B′) C + (A ⊕ B) C′ = ABC + A′B′C + AB′C′ + A′BC′ [As: X + X = X] [So, A′B′C + A′B′C = A′B′C] = ABC + (A′B′C + A′B′C) + AB′C′ + A′BC′ This can be written as: = ABC + A′ (B ⊕ C) + B′ (A ⊕ C)This explanation has been provided by Saksham Seth.
Question 82 
Using Booth's Algorithm for multiplication, the multiplier 57 will be recoded as
0 1 0 0 1 0 0 1  
1 1 0 0 0 1 1 1  
0 1 0 0 1 0 0 0
(A+B+C)(A¯+B¯+C)
ABC+A¯(B⊕C)+B¯(A⊕C)  
0 1 0 0 1 0 0 1 
Discuss it
Question 83 
How many pulses are needed to change the contents of a 8bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?
134  
133  
124  
123 
Discuss it
Question 83 Explanation:
8 bit Counter range 0255
To go from 10101100 (172) to 00100111 (39)
 first counter will move from 172 to 255(255172=83)
 255 to 0=1 pulse
 and then 0 to 39(390=39).
Question 84 
Which of the following input sequences will always generate a 1 at the output z at the end of the third cycle?
0 0 0
1 0 1
1 1 1  
1 0 1
1 1 0
1 1 1  
0 1 1
1 0 1
1 1 1  
0 0 1
1 1 0
1 1 1 
Discuss it
Question 84 Explanation:
Let's take cycles as 1,2,3. There are two flipflops, let's call them D1 and D2. And Q1, Q2 to be the output for flipflop D1, D2 respectively. here Q11 means output of D1 flipflop for 1st cycle, similarly Q12 is the output of D1 flipflop for 2nd Cycle. A1, A2, A3 means input for A at cycles 1, 2, 3 respectively. Similarly for B and C. Let's check for the option D where: A1=0 A2=1 A3=1 B1=0 B2=1 B3=1 C1=1 C2=0 C3=1 Q11=0 Q12 = A1.B1 = 0.0 = 0 Q13 = A2.B2 = 1.1 = 1 ~Q11=1 ~Q12 = ~(A1.B1) = 1 ~Q13 = ~(A2.B2) = 0 Q21 = 0 Q22 = C1.(~Q11) = 1.1 = 1 Q23 = C2.(~Q12) = 0.1 = 0 Z1 = 0 Z2 = Q12.Q21 = 0.0 = 0 Z3 = Q13.Q22 = 1.1 = 1 Hence, sequence given in option D is generating a 1 at the output z at the end of the third cycle (Z3).This explanation has been contributed by Harshit Sidhwa.
Question 85 
The circuit shown below implements a 2input NOR gate using two 24 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?
1, 0, B  
1, 0, A  
0, 1, B  
0, 1, A 
Discuss it
Question 85 Explanation:
In MUX1, equation is : g = Az + Bz’ In MUX2, equation is : f = xg + yg’ = x(Az + Bz’) + y (Az + Bz’)’
Function ‘f’ should be equal to (A + B)’ .
Using hit and try method, put x = 0, y = 1 and z = A. f = 0(AA + BA’) + 1(AA + BA’)’ f = (A + A’B)’ f = (A + B)’
Thus, option (D) is correct.
Please comment below if you find anything wrong in the above post.
Question 86 
We want to design a synchronous counter that counts the sequence 010203 and then repeats. The minimum number of JK flipflops required to implement this counter is
Note : This question was asked as Numerical Answer Type.
1  
2  
4  
5 
Discuss it
Question 86 Explanation:
Total 4.
2 JK flip flops for synchronous counter + 2 JK flipflop to make 2 bit counter.
Actually, when we are repeating again then after 3 we don't know that our Synchronous counter will go to which zero.
To make it work right, we need to move it to
1st zero after 3
2nd zero after 1
3rd zero after 2
i.e. 0 > 1 > 0 > 2 > 0 > 3 (from here it again go to 1st zero).
In order to decide which zero to move on we use counter from 1 to 3, I have attached truth table of normal 2 bit synchronous counter using JK flip flop.
// This Explanation has been contributed by Mohit Gupta
Question 87 
Consider the two cascaded 2to1 multiplexers as shown in the figure.
The minimal sum of products form of the output X is
A  
B  
C  
D 
Discuss it
Question 87 Explanation:
Assume P=0 and Q=0
The output should be R'
Only option D satisfies this case.
Hence, D is the correct choice.
Question 88 
Consider a carry lookahead adder for adding two nbit integers, built using gates of fanin at most two. The time to perform addition using this adder is
Θ(1)  
Θ(Log (n))  
Θ(√ n)  
Θ(n) 
Discuss it
Question 88 Explanation:
Look ahead carry generator gives output in constant time if fanin = number of inputs.
For Example:
It will take O(1) to calculate c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0, if OR gate with 5 inputs is present.And, if fanin != number of inputs then we will have delay in each level, as given below. If we have 8 inputs, and OR gate with 2 inputs, to build an OR gate with 8 inputs, we will need 4 gates in level1, 2 in level2 and 1 in level3. Hence 3 gate delays, for each level. Similarly an ninput gate constructed with 2input gates, total delay will be O(log n). // This Explanation has been provided by Saksham Raj Seth.
Question 89 
Consider an eightbit ripplecarry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _____________
[This Question was originally a Fillintheblanks Question]
1  
2  
1  
2 
Discuss it
Question 89 Explanation:
Here "longest latency for the sum to stabilize" means maximum delay that ripple carry adder would take to add A and B, we are given value of A and need to find the value of B. The Delay in Ripple Carry Adder is as follows  For sum there are 2 XOR gates.  For carry there is 1 XOR,1 AND and 1 OR gate. i.e total 3 gate delays in case of carry and 2 gate delays in sum.
If we do 2's complement of 1 in 8 bit we get "00000001". same we do for each option 1 : "11111111" 2 : "00000010" 1 : "00000001" 2 : "11111110"So in case of 1 the carry bit will change and thus it will take 1 extra gate delay, hence we could see that the maximum delay we could get when input at B will be 1, i.e. add "00000001" with "11111111" and would get Maximum delay. This explanation has been provided by Harshit Sidhwa.
Question 91 
Let X be the number of distinct 16bit integers in 2’s complement representation. Let Y be the number of distinct 16bit integers in sign magnitude representation. Then X −Y is _________
[This Question was originally a Fillintheblanks Question]
1  
2  
3  
0 
Discuss it
Question 91 Explanation:
For n bits, Distinct values represented in 2's complement is 2^n1 to 2^n1 1
Distinct values represented in Signed Magnitude is (2^(n1) 1) to 2^(n1) 1
For example if n = 8, we can represent numbers from 128 to 127 in 2's complement representation and numbers from 127 to 127 in signed magnitude representation.
Difference is 1. The difference of 1 is there because there are two different representations of +0 and 0 in signed magnitude representation. But in 2's complement representation, there is one representation of 0.
Question 92 
The addition of 4bit, two's complement, binary numbers 1101 and 0100 results in
0001 and an overflow  
1001 and no overflow  
0001 and no overflow  
1001 and an overflow 
Discuss it
Question 92 Explanation:
Its 3+4=1, so no overflow
So Answer is C.
Question 93 
Which of the following input sequences for a crosscoupled RS flipflop realized with two NAND gates may lead to an oscillation ?
11, 00  
01, 10  
10, 01  
00, 11 
Discuss it
Question 93 Explanation:
RS flip flop using NAND gates. So, 00 input causes indeterminate state which MAY lead to oscillation.
Question 94 
The following circuit implements a twoinput AND gate using two 21 multiplexers.
What are the values of X_{1}, X_{2}, X_{3}?
What are the values of X_{1}, X_{2}, X_{3}?
X_{1}=b, X_{2}=0, X_{3}=a  
X_{1}=b, X_{2}=1, X_{3}=b  
X_{1}=a, X_{2}=b, X_{3}=1  
X_{1}=a, X_{2}=0, X_{3}=b 
Discuss it
Question 95 
The following bit pattern represents a floating point number in IEEE 754 single precision format
1 10000011 101000000000000000000000
The value of the number in decimal form is
10  
13  
26  
None of these 
Discuss it
Question 95 Explanation:
To convert the floating point into decimal, we have 3 elements in a 32bit floating point representation:
i. Sign
ii. Exponent
iii. Mantissa
Sign bit is the first bit of the binary representation. '1' implies negative number and '0' implies positive number Exponent is decided by the next 8 bits of binary representation. 131127=4
Hence the exponent of 2 will be 4. i.e 2^{4}=16.
127 is the unique number for 32 bit floating point representation. It is known as bias. It is determined by 2^{k1}1 where 'k' is the number of bits in exponent field.
Thus bias = 3 for 8 bit conversion and 127 for 32 bit. (2^{81}1 = 1281=127)
Mantissa is calculated from the remaining 24 bits of the binary representation. It consists of '1' and a fractional part which is determined by:
The fractional part of mantissa is given by:
1*(1/2) + 0*(1/4) + 1*(1/8) + 0*(1/16) +.........=0.625
Thus the mantissa will be 1+0.625=1.625
The decimal number hence given as
Sign*Exponent*Mantissa = (1)*(16)*(1.625) = 26.
Related :
https://www.youtube.com/watch?v=03fhijH6e2w
http://quiz.geeksforgeeks.org/numberrepresentation/
This solution is contributed by Kriti Kushwaha.,
Question 96 
xz+x'z'  
xz'+x'z  
x'y'+yz  
xy+y'z' 
Discuss it
Question 97 
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:
1, 1, 0  
1, 0, 0  
0, 1, 0  
1, 0, 1 
Discuss it
Question 97 Explanation:
01001101
+11101001

100110110
carry flag =1
overflow happens only when two same sign numbers are added and carry generated is different from both added numbers.
so, overflow flag = 0,
sign bit = 0
+11101001

100110110
carry flag =1
overflow happens only when two same sign numbers are added and carry generated is different from both added numbers.
so, overflow flag = 0,
sign bit = 0
Question 98 
Consider the following state diagram and its realization by a JK flip flop
The combinational circuit generates J and K in terms of x, y and Q.
The Boolean expressions for J and K are :
The combinational circuit generates J and K in terms of x, y and Q.
The Boolean expressions for J and K are :
(x⊕y)'and x'⊕y'  
(x⊕y)'and x⊕y  
x⊕y and (x⊕y)'  
x⊕yand x⊕y 
Discuss it
Question 99 
AB’C + ABC’
 
A’B’C + A’BC’
 
A’BC + A’B’C’
 
ABC + AB’C’ 
Discuss it
Question 99 Explanation:
The output of a multiplexer (2X1) can be expressed in the form of:
f= S’. L1 + S. L2
For the above diagram the output from the first multiplexer would be B’C + BC’ which acts a select line for the second multiplexer. Hence,
f= (B’C + BC’)’A + (B’C + BC’).0
= ((B’C)’ . (BC’)’)A + 0
= (B+C’)(B’ + C)A
= (BC + B’C’) A
= ABC + AB’C’
f= S’. L1 + S. L2
For the above diagram the output from the first multiplexer would be B’C + BC’ which acts a select line for the second multiplexer. Hence,
f= (B’C + BC’)’A + (B’C + BC’).0
= ((B’C)’ . (BC’)’)A + 0
= (B+C’)(B’ + C)A
= (BC + B’C’) A
= ABC + AB’C’
Question 100 
The complement of the function F = (A + B’)(C’ + D)(B’ + C) is:
A’B + CD’ + BC’
 
AB’ + C’D + B’C
 
AB’ + CD’ + BC
 
AB + BC + CD 
Discuss it
Question 100 Explanation:
Using Demorgan’s Law (Break the line, change the sign)
Complement of
F = F’ = ((A + B’)(C’ + D)(B’ + C))’
F’ = ((A + B’))’ + ((C’ + D))’ + ((B’ + C))’
F’ = A’B + CD’ + BC’
Complement of
F = F’ = ((A + B’)(C’ + D)(B’ + C))’
F’ = ((A + B’))’ + ((C’ + D))’ + ((B’ + C))’
F’ = A’B + CD’ + BC’
Question 101 
Which of the following is false:
Digital signature is used to verify that a message is authentic.  
Digital certificate is issued by a third party.  
Digital certificate ensures integrity of the message.  
Digital signature ensures nonrepudiation. 
Discuss it
Question 101 Explanation:
Digital certificate only verifies the identity of the user for whom the digital certificate is issued.
There are 101 questions to complete.