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GATE | GATE-CS-2001 | Question 33
Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0. ![\"GATECS2001Q33\"](\"https://cdncontribute.geeksforgeeks.org/wp-content/uploads/GATE-CS-2001-Question-33.jpg\")
Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y? 
(A)
a
(B)
b
(C)
c
(D)
d
Answer
Please comment below if you find anything wrong in the above post
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